The present invention relates to a dynamic read/write memory for refreshing storage data in a normal data read/write cycle and, more particularly, to an improvement of a control circuit for controlling word lines or a column decoder for such a memory.
A so-called pseudo static RAM (to be referred to as a PSRAM hereinafter) is known as a RAM which uses memory cells (e.g., each comprising one transistor and one capacitor) requiring refreshing of storage data, which does not require the complicated timing signals used in a dynamic RAM, such as a column address strobe signal (CAS) and a row address strobe signal (RAS), and which can be used in the same manner as a normal static RAM. The refreshing operation must be performed before or after the normal read/write cycle in a conventional PSRAM. Refreshing timings must be set by a user, which can be inconvenient.
Assume that data is refreshed during address decoding or at the end of read/write access, i.e., that data refreshing is performed in parallel with data read/write access in one cycle. FIG. 1 shows a schematic arrangement of a dynamic read/write memory (DRAM), and FIGS. 2A to 2I are timing charts for explaining the operation of the DRAM. It is also assumed that a pair of bit lines BL and BL are precharged.
If address input signal ADD (FIG. 2A) is changed, or when a chip enable signal (not shown in FIG. 2) is input, a memory operation cycle is initiated. The change in signal ADD causes an address decoder (not shown) to select one word line WL1, and corresponding signal NWL1 (FIG. 2B) becomes "H". Storage data in memory cell 51 and data in dummy cell 52 are read out onto a pair of bit lines BL and BL (FIG. 2G), and a slight potential difference occurs between the bit lines. Sense amplifier 53 is then operated in response to sense enable signal SAE (FIG. 2C), and the potential difference is amplified by amplifier 53. Subsequently, column decoder 54 is operated in response to column decoder enable signal CDE (FIG. 2E), and data signals on the bit lines BL and BL are decoded. The decoded signals appear on a pair of data lines DL and DL (FIG. 2H). The data signals on the lines DL and DL are waveshaped by input/output circuit 55. As a result, the waveshaped signals are output as active data from data input/output terminal I/O (FIG. 2I).
Signal CDE is supplied as a pulse signal to decoder 54 and becomes "L" after input/output circuit 55 latches active data. When signal CDE becomes "L", signal NWL1 becomes "L" to render line WL1 inoperative. Amplifier 53 is then disenabled in response to "L" of signal SAE, and lines BL and BL are precharged.
Refreshing drive signal RWL2 (FIG. 2D) is supplied to word line WL2 to render sense amplifier 53 operative, and data is rewritten in memory cell 51. During the refreshing operation, data need not be output from the memory. Signal CDE is kept "L", and column decoder 55 is kept inoperative. In this case, the active data latched by input/output circuit 55 appears at terminal I/O.
The word lines (WL1, WL2) are driven in response to pulses as described above, and thus the refreshing operation can be performed in one cycle.
The present inventors developed a control circuit for switching between normal data read/write access (to be referred to as a normal operation hereinafter) and refreshing operation. The control circuit is shown in FIG. 3. In this circuit, normal operation request signal NREQ is generated by reset-set flip-flop (RS FF) 61 which is set in response to normal operation start instruction signal NSET and is reset in response to normal operation end instruction signal NRST. Refreshing operation request signal RREQ is generated by RS FF 62 which is set in response to refreshing operation start instruction signal RSET and is reset in response to refreshing operation end instruction signal RRST. Signals NREQ and RREQ are supplied as input signals to signal selection circuit 65 constituted by NAND gates 63 and 64.
An output signal from NAND gate 63 is inverted by inverter 66, and normal operation control circuit 67 is operated in response to output signal NGO from inverter 66. Similarly, an output signal from NAND gate 64 is inverted by inverter 68, and refreshing operation control circuit 69 is rendered operative in response to output signal RGO from inverter 68. In this manner, the normal and refreshing operations are switched.
The word lines are driven by control circuits 67 and 69, in response to pulses as described above. In the normal operation, particularly in the data write mode, the following problem occurs. This problem will be described with reference to the timing charts in FIGS. 4A to 4E.
Assume that write enable signal WE rises at time t0 in FIG. 4B. In this case, the circuit in FIG. 3 generates normal operation request signal NREQ and causes normal operation word line drive signal NWL1 on word line WL1 to become "H". It is further assumed that the refreshing operation has already started at time t0. At time t1, when signal RWL becomes "L" after the refreshing operation is completed, signal NWL1 (FIG. 4C), corresponding to address input signal ADD (FIG. 4A), becomes "H", and data write access is initiated. In this case, a period t(WR) (FIG. 4A) between the leading edge of write enable signal WE and the next change in signal ADD becomes long. Thus, the one-cycle period of the DRAM is undesirably prolonged, only in the write mode. In other words, when a refreshing operation is performed in the normal operation in the above-mentioned DRAM control circuit, the data write cycle time is undesirably prolonged.